Electronic parts of various kinds are usually mounted at selected positions on copper wiring patterns formed on a printed circuit board and are soldered to form electronic circuit wirings. In a conventional electronic circuit, a solder layer containing Pb (lead) as a main component has been used to join an electronic device on a printed circuit board of paper phenol resin, epoxy resin, glass epoxy resin, or the like.
Patent Reference 1 discloses a semiconductor mounting circuit board in which an insulating filler is applied on a metal base substrate to be patterned thereon with aluminum (Al), copper (Cu) or the like forming a circuit to achieve high-density implementing of semiconductors on the circuit board. In the board described in this Reference, silica containing epoxy resin of 100 μm thickness is used as the insulating filler on which a foil of aluminum and copper is formed as a wiring layer.
Patent Reference 2 discloses a metal thin film laminate ceramic board in which conductive layers of such as Cu are applied on a ceramic substrate of AlN. Of this metal thin film laminate ceramic board, the conductive layers are patterned to form a circuit used in an IC package.
However, solders containing lead and tin (Sn) tend to be restricted from use in recent years for reducing environmental load. Especially in Europe, their usages have been banned by the RoHS Directive (directive of the European Assembly and Directorate on restriction of the use of certain hazardous substances in electrical and electronic equipments) since Jul. 1, 2006. Consequently, lead free solders such as those formed of Au—Sn, Ag—Sn, In—Sn, Zn—Sn and Bi—Sn have been proposed as alternatives of the lead and tin containing solders.
Nonpatent Reference 1 reports that when a solder if not containing lead is left at room temperature, it takes more than 10 months for equilibrium to be reached. Nonpatent Reference 2 reports that when a load by a heat cycle is applied after solder bonding in semiconductor laser package using a solder not containing lead, the strength of the solder bonding changes gradually due to that heat cycle load.
For example, when an electrode layer made of gold (Au) is formed on a substrate as an uppermost layer and a device is bonded to a solder layer on the electrode layer using a lead free solder such as Au—Sn to form the solder layer, the solder layer by being heated melts once and is then allowed to harden by rapid cooling after the device is bonded. In this case, the solder that makes up the solder layer is apt to become non-equilibrial and to cause the solder layer to melt while bonding to the device. Their initial bonding strength, that is the strength of bonding between the solder layer solidified and the device bonded thereto, becomes unstable. FIG. 29 is a phase diagram illustrating phases by atomic percent of alloy consisting of Au and Sn (Au—Sn alloy) (see Nonpatent Reference 3).
Patent Reference 3, by the present inventors, discloses a submount that allows a solder protective layer disposed on the surface of a solder to be melted readily at a reduced bonding temperature by improving solubility of the solder and reducing its complete dissolution temperature, thereby to permit forming a solder joint having low thermal stress.
References Cited:
Patent Reference 1: Japanese Patent, JP 3156798 B;
Patent Reference 2: Japanese Patent, JP 2762007 B;
Patent Reference 3: Japanese Patent Laid Open Application, JP 2006-288463 A;
Nonpatent Reference 1: V. SIMIC and Z. MARINKOVIC, “Thin film interdiffusion of Au and Sn at room temperature”, J. Less-Common Metals, 51, pp. 177-179, 1977;
Nonpatent Reference 2: J-H. Kuang and five others, “Effect of Temperature Cycling on Joint Strength of PbSn and AuSn Solders in Laser Packages”, IEEE Trans., Adv. Pack, Vol. 24, No. 4, pp. 563-568, 2001; and
Nonpatent Reference 3: (Japanese) “Metal Data Book” compiled by the Japan Institute of Metals, revised 3rd Edition, MARUZEN, p. 410, Mar. 25, 1993.